This application claims the priority benefit of Taiwan application serial no. 91103242, filed Feb. 25, 2002.
1. Field of the Invention
The invention relates in general to a bumping process. More particularly, the invention relates to a bumping process where bumps are transferred onto a wafer using a bump transfer substrate with a release layer.
2. Description of the Related Art
Recently, following the changes in electronics technology with each passing day, high-tech electronic products with multi-functions have been presented to the public one after another. Within the integrated circuit industry there is a continuing effort to increase integrated circuit speed as well as device density. As a result of these efforts, there is a trend towards using the following technologies, such as ball grid array (BGA) package, flip chip (F/C) package, chip-scale package (CSP), multi-chip module (MCM) and so on, when packaging complex high-speed integrated circuits. As far as the flip chip technology is concerned, bumps are used to electrically connect a chip to a substrate, whereby the electrical distance between the chip and the substrate is relatively short to benefit increasing signal transfer speed. Besides, there can be relatively many electrical connections formed on the chip. Therefore, using bumps to connect a chip to a substrate is a main trend within the high-density package field.
FIGS. 1-4 are schematic cross-sectional views showing a conventional bumping process. Referring to FIG. 1, a wafer 100 is provided with electrical connections 102 (only one of them is shown) and a passivation layer 104. The passivation layer 104 is deposited on the surface layer of the wafer 100 to protect the wafer 100. The passivation layer 104 has openings 105 (only one of them is shown) exposing the electrical connections 102 respectively. Following, an adhesion layer 106a, a barrier layer 106b and a wettable layer 106c are sequentially formed over the wafer 100.
Next, referring to FIG. 2, over the wafer 100 is formed a photoresist layer 108 having many openings 109 (only one of them is shown) exposing the wettable layer 106c deposited on the electrical connections 102. Subsequently, an electroplating process or a screen-printing process is used to fill solder paste into the openings 109 of the photoresist layer 108 to form solder posts 110 (only one of them is shown).
Next, referring to FIG. 3, after the solder posts 110 are formed, the photoresist layer 108 is removed. Following, the adhesion layer 106a, the barrier layer 106b and the wettable layer 106c not covered by the solder posts 110, serving as etching mask, are removed. The defined adhesion layer 106a, the barrier layer 106b and the wettable layer 106c are called an under-bump-metallurgy layer 106 (UBM).
Finally, referring to FIG. 4, after the under-bump-metallurgy layer 106 is defined, a reflow process is performed to turn the solder posts 110 into ball-like shaped bumps 112.
In the above conventional bumping process, a photolithography process is performed to define the bump location on the chip. However, the photolithography process includes the complicated steps of dehydration baking, priming, photoresist-layer coating, soft-baking, exposing, post-exposure baking, developing, hard-baking, etching and so on. As a result, to define the bump location by the photolithography process is time consuming and costly.
It is an objective according to the present invention to provide a bumping process where it is not necessary to perform a photolithography process during formation of bumps onto a substrate, such as wafer, printed circuit board (PCB), carrier and so on.
To achieve the foregoing and other objectives, the present invention provides a bumping process where a bump transfer substrate is provided with a release layer on which many bumps to be transferred are provided. A substrate is provided with many electrical connections thereon. Subsequently, the bumps on the bump transfer substrate are pressed onto the electrical connections of the substrate accompanying a heating process and then the bumps are transferred onto the electrical connections of the substrate because the adhesion characteristic between the bumps and the electrical connections is better than that between the bumps and the release layer.
According to the bumping process of the present invention, such bumps are made of various material as gold, tin-lead alloy and so on, and can be transferred onto the substrate, for example, wafer, printed circuit board, carrier, etc.
If the bumps are transferred onto a wafer, the adhesion characteristic between the bumps and the electrical connections on the wafer should be better than that between the bumps and the release layer.
If the bumps are transferred onto a printed circuit board or onto a carrier, the adhesion characteristic between the bumps and the electrical connections on the printed circuit board or on the carrier should be better than that between the bumps and the release layer.
According to the bumping process of the present invention, the bumps have a bad adhesion onto the release layer on the bump transfer substrate, wherein the material of the release layer is, for example, chromium.
According to the bumping process of the present invention, after the bumps are transferred onto the electrical connections of the substrate, a reflow process is performed.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.